Fpga-based Phasor Measurement Unit Protype

Résumé: Phase measurement is required in electronic applications where a synchronous relationship between the signals needs to be preserved. As the world continues to move towards a Smarter Grid day by day, it has become the necessity to incorporate real-time monitoring of the grid wherein the instantaneous snapshot of the health of the grid can be made available. Traditional electronic system which are used for time measurement are designed using a classical mixed-signal approach. With the advent of recon?gurable hardware such as ?eld-programmable gate arrays (FPGAs), it is more advantageous for designers to opt for all-digital architecture. This project is about the design and implementation of a part of Phasor Measurement Unit (PMU) Prototype based on FPGA. It discusses how an FPGA can be used to estimate the phasors of a one-phase system. An example sinusoidal input signal is generated by a Function Generator and then sampled using the Analog to Digital Converters (ADC) on the FPGA board. The design then stores digital data into a local FIFO, which is passed to a 1024- Point FFT hardware core to get the spectrum of the signal and hence calculate the frequency and the phase difference. The system uses the Intel DE10 FPGA board (donated by the Intel University Program) and the Quartus Prime suite to design and implement the system. One of the aims of this project is to evaluate the potentials of the newly acquired DE10 FPGA board. The final output of the FFT core are transmitted back to local host through Quartus SignalTap II logic Analyzer Tool.

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